//Register File, by Alejandro Lizaola, DCI

module File_Register(clk,arst,Din,Dout,rd_register1,rd_register2,wr_register,wr_data,Reg_write,Reg_rd,rd_data1,rd_data2);
  input arst;
  input [4:0]rd_register1;
  input [4:0]rd_register2;
  input [4:0]wr_register;
  input [31:0]wr_data;
  input [31:0]Din;
  input clk;
  input Reg_write,Reg_rd;
  output wire[31:0]Dout;
  output[31:0]rd_data1;
  output[31:0]rd_data2;
  
  reg [31:0]reg_array[0:31];
  
  always @(posedge clk)
  begin 
   reg_array[0] <= 32'h00_00_00_00; 
   reg_array[5] <= 32'b00000000_00000000_00000000_0010_1011;
   reg_array[6] <= 32'b00000000_00000000_00000000_0010_1101;
    if (Reg_write && (wr_register != 30))
      begin
        reg_array[wr_register] <= wr_data;
      end
    if (Reg_rd && !Reg_write)
      reg_array[30] <= Din; //Puerto de entrada, solo lectura
    end
    
    assign rd_data1 = reg_array[rd_register1];
    assign rd_data2 = reg_array[rd_register2];
    assign Dout = reg_array[31]; //Puerto de salida, solo escritura
  endmodule

        
